(1) Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, such as an EPROM (Erasable and Programmable Read Only Memory) and an EEPROM (Electrically Erasable and Programmable Read Only Memory), which memory device is provided with non-volatile memory cell transistors.
If the cost of a non-volatile semiconductor memory device can be reduced, the non-volatile semiconductor memory device can be substituted for a floppy disk unit, a hard disk unit and the like and used as an auxiliary memory unit for a computer system. The non-volatile semiconductor memory device having a large capacity can be made using a fine patterning process, so that the cost of the non-volatile semiconductor memory device can be reduced. In addition, the processing speed of CPUs (central processing units) in computer systems is gradually increasing. Thus, a high-speed non-volatile semiconductor memory is desired.
(2) Description of the Related Art
FIG. 1 shows an essential part of a conventional EPROM which is one of the types of non-volatile semiconductor memory- Referring to FIG. 1, a cell-transistor 1 is connected between a word line 2 and a bit line 3. The bit line 3 is connected to a bus line 6 via a bit selecting transistor 4 (an n-MOS transistor). A word line selecting signal X is supplied to the gate of the cell-transistor 1 via the word line 2. A bit line selecting signal Y is supplied to the gate of the bit selecting transistor 4. Actually, a plurality of bit lines are connected to the bus line 6 via bit selecting transistors and a plurality of cell-transistors form a memory cell in the EPROM. For the sake of simplicity, FIG. 1 shows only the single cell-transistor 1 and the single bit line 3 connected with the cell-transistor 1.
The bus line 6 is included in a sense amplifier 5. In the sense amplifier 5, a resistor 11 is connected between a power line 7 (Vcc:e.g. +5V) and the drain of a transistor 9 (an n-MOS transistor). The gate and source of the transistor 9 are respectively connected to the bus line 6 and a ground line. A load transistor 13 (a p-MOS transistor) is connected between a power line 8 (Vcc:e.g. +5V) and the drain of a transistor 10 (an n-MOS transistor). The source of the transistor 10 is connected to the bus line. 6. A resistor 12 is connected between the bus line 6 and the ground line. Both the drain and the gate of the load transistor 13 are connected to an output terminal 14.
Data "1" stored in the cell-transistor 1 is read out as follows. When the bit line selecting signal Y and the word line selecting signal X are activated, a current flows through the cell-transistor 1. In this case, the voltage of the bus line 6 decreases and the on-resistance of the transistor 9 increases, so that the voltage level at a node 15 connected to the gate of the transistor 10 increases. Thus, the transistor 10 is turned on and a current flows through the load transistor 13. As a result, the level of the output voltage Vout at the output terminal 14 decreases. That is, the output voltage Vout has a low level corresponding to the data "1".
Data "0" stored in the cell-transistor 1 is read out as follows. When the bit line selecting signal Y and the word line selecting signal X are activated, no current flows through the cell-transistor 1. In this case, the voltage level of the bus line 6 is maintained at a high level, so that the transistor 10 is maintained in an off-state. Thus, the output voltage Vout at the output terminal 14 has a high level corresponding to the data "0" and is maintained in this state.
In a case where the data stored in the cell-transistor 1 is read out, the bus line 6 must have been charged to a predetermined voltage level. However, if the above read operation of the cell-transistor 1 is performed under a condition in which the voltage level of the bus line 6 is greater than 1.5 [V], a situation occurs in which electrons are injected into the cell-transistor 1. In this case, the data stored in the cell-transistor 1 is corrupted. This corruption of data stored in the cell-transistor 1 is often referred to as a soft error. In the conventional EPROM shown in FIG. 1, the bus line 6 is charged by the load transistor 13 and the voltage of the bus line 6 is maintained at a 1 [V] level by operations of the transistors 9 and 10. That is, circuit constants of the EPROM are set so that, when the level of the bus line 6 exceeds 1 [V], the voltage level at the node 15 decreases and the transistor 10 is turned off. As a result, the voltage level of the bus line 6 is maintained at 1 [V].
However, when the voltage level of the bus line 6 nears 1v, the transistor 10 nears the off state so that the amount of current flowing through the transistor 10 decreases. As a result, it takes a long time to charge the bus line 6 until the voltage level thereof reaches 1 [V], as shown in FIG. 2. Thus, either when the state of the EPROM changes from a stand-by state where no voltage is applied to the bit line 3 to an active state where the voltage is applied to the bit line 3, or when address signals (including the bit line selecting signal Y and the word line selecting signal X) are switched to the active state, it is difficult to rapidly charge the bus line 6 to a predetermined voltage level (e.g. 1 [V]). That is, it is difficult to obtain high-speed operation of the EPROM.